1. Field
Embodiments of the present disclosure relate to a data receiver that simultaneously receives a data signal and a data strobe signal for sampling the data signal, and more particularly, to a data receiver that samples a data signal by generating a sampling clock signal from an internal clock signal using a data strobe signal.
2. Description of the Related Art
An example of a device that receives a data signal and a data strobe signal for sampling the data signal may include a memory device and a memory controller.
FIG. 1 is a block diagram illustrating a conventional memory controller 10 and a memory device 20.
The conventional memory controller 10 receives a data strobe signal DQS and a data signal DQ from the memory device 20, samples the data signal DQ according to the data strobe signal DQS, and determines a logic level of the data signal DQ.
The conventional memory controller 10 includes a delay locked loop (DLL) 11, a delay line 13, and a sampler 12. The DLL 11 receives the data strobe signal DQS and generates a sampling clock signal SCLK. The delay line 13 delays the data signal DQ. The sampler 12 samples a signal outputted from the delay line 13 according to the sampling clock signal SCLK.
FIG. 2 is a block diagram illustrating the DLL 11 of FIG. 1.
The DLL 11 includes a phase comparator 1, a filter 2, and a variable delay line 3. The phase comparator 1 compares a phase of the data strobe signal DQS with a phase of the sampling clock signal SCLK and outputs a control signal PD. The filter 2 outputs a delay control signal DCON based on the control signal PD outputted from the phase comparator 1. The variable delay line 3 delays the data strobe signal DQS in response to the delay control signal DCON, and outputs the sampling clock signal SCLK.
Referring back to FIG. 1, the DLL 11 may sample the data signal DQ by changing the phase of the data strobe signal DQS by 90 degrees. For this operation, the phase comparator 1 may compare a phase of the sampling clock signal SCLK with a phase of a signal obtained by delaying the phase of the data strobe signal DQS by 90 degrees.
While the signal delayed by 90 degrees through the DLL 11 is provided to the sampler 12, the delay line 13 delays the data signal DQ by a delay amount and provides the delayed data signal to the sampler 12. Through the above operation, the data signal DQ and the sample clock signal SCLK, which are inputted to the sampler 12, may have a phase difference of 90 degrees.
When a data transmission rate is increased, the conventional memory controller 10 activates the DLL 11 and the delay line 13 in order to lock the delay of the data signal DQ and the data strobe signal DQS. However, it is difficult to precisely adjust the timing using the DLL11 and the delay line 13. Furthermore, for this structure, the size of the circuitry may be further increased.
The memory controller 10 and the memory device 20 have been taken as an example for description. However, the above-described problem commonly occurs in a data receiver that receives a data signal and a data strobe signal at the same time.